The invention relates in general to a mounting device and method of use for an integrated circuit chip package.
Specfically, the invention relates to castellated chip carriers and their assembly with other electrical components such as other chip carriers, printed circuit boards and the like.
The term "castellated chip carrier" as used herein refers to devices, usually ceramic, used in the electronics industry to mount integrated circuit chips in order to mount them on other electrical components such as printed circuit boards. The chip carrier has a number of fine contact points to which the integrated circuit chip contact points are connected. The carrier contains a number of larger contact pads electrically interconnected with the fine contact points. The pads are typically around the edge or periphery of the chip carrier and are used to connect the chip carrier to the other electrical components such as the printed circuit board. The number of contact pads around the periphery of the chip carrier is typically 24, 44, 52, 68 or other number as dictated by the chip to be mounted on the chip carrier.
The term "castellation" as used herein refers to the vertical grooves along the peripheral edge of the ceramic chip carrier. The castellations are formed by punching holes in the ceramic material from which the chip carrier is made. The holes are uniformly spaced over the range of chip carrier sizes. The ceramic material is then cut or broken along the center line of those holes to form the individual chip carrier. Since the castellations are in effect the remains of the precisely formed holes which are also precisely positioned relative to the contact pads at the periphery of the chip carrier, the castellations are particularly useful in the instant invention in positioning and aligning the chip carrier to connect it with other electrical components.
The remaining portions along the edge of the chip carrier which are cut or broken to form the individual chip carrier are not always precise with respect to the positioning of the individual connection pads at the periphery of the chip carrier. Therefore, these remaining rough edges cannot always be used to provide precise positioning and alignment of the chip carrier with respect to connection to other electrical components.
The mounting devices and methods heretofore provided for such chip carriers generally have been of relatively complicated and expensive construction. These devices have not been readily adaptable for the range of sizes of chip carriers.